1. Field of the Invention
The present invention relates to a field of semiconductor integrated circuit manufacturing, and more specifically, to a method of handling a thin wafer during processing.
2. Discussion of Related Art
Gordon Moore originally observed in 1964 that technology innovation had led to a doubling of a density (number of transistors per unit area) of an integrated circuit (IC) chip approximately every 12 months. By 1975, the trend had stabilized to a doubling of the density about every 18 months. Over the ensuing decades, the semiconductor industry has adhered closely to a well-known Moore's Law in increasing the density of transistors for each generation of IC chips.
The IC chip includes a planar transistor that is formed in a substrate, such as a wafer. The wafer is made from a semiconductor material, such as silicon. During processing, a material may be added to, or removed from, the wafer. The material may include an insulator, such as silicon oxide, or a conductor, such as copper.
Additive processes that are used to form material, partially or completely, on the wafer include chemical vapor deposition, sputtering, electroplating, oxidation, and ion implantation.
Subtractive processes that are used to remove material, partially or completely, from the wafer include wet etching, dry etching, and chemical-mechanical polishing (CMP).
For many layers of material, photolithographic processes are used, in conjunction with the additive processes or the subtractive processes, to pattern portions of the wafer.
Maintaining an aggressive schedule required to comply with Moore's Law has resulted in a scaling down of a metal oxide semiconductor field effect transistor (MOSFET) that is used in a complementary metal-oxide-semiconductor (CMOS) circuit. The performance and reliability of the transistor have been improved by implementing many features such as semiconductor-on-insulator (SOI) substrate, selective epitaxially deposited (SED) raised source and drain, atomic layer deposited (ALD) high-k (dielectric constant) gate dielectric, metal gates, strained channel, and low-k interlevel dielectric (ILD) layers.
Many parameters of the IC chip are monitored during fabrication to ensure that the product specification for performance and reliability will be met even as the design rule becomes tighter. However, as the wafer size becomes larger, such as a diameter of 450 mm, challenges may arise in handling and transporting the wafer without incurring any damage. The difficulty may be aggravated for thin wafers that are required for die stacking, wafer stacking, 3-dimensional (3-D) packaging, and attaching thin flip chip die to thin and flexible substrates.